Reducing power dissipation is an important concern in processor and circuit design. Increases in the density of microelectronic devices and the related need to minimize the heat generated by such devices provides one major impetus for such reduction. Reducing the amount of power dissipated at a microelectronic level can greatly reduce excess heat that may adversely impact both a product's performance and lifespan. The need to minimize power usage in mobile electronics and other battery-operated devices further provides impetus for reducing power dissipation. Additionally, the introduction of specialized circuitry to processors and other circuits prompts heightened concern about power dissipation. Such circuits, while providing improved performance and increased functionality, generally dissipate comparatively large amounts of power.
From the standpoint of processor or circuit design, a number of techniques have been used to reduce power usage. These techniques can be grouped into two basic strategies. First, the processor's circuitry is designed to use less power. Second, the processor is designed in a manner that permits power usage to be managed.
In the past, managing power usage has been primarily at the system level. Various "power down" and "sleep" modes have been implemented that permit large system components such as a disk drive, display, or the processor itself, to be intermittently powered down. Other application specific circuits or general processors have been introduced which similarly engage "stand by" modes wherein the majority of system level components in an application specific circuit or general processor are shut down while waiting for a real time interrupt or event. For example, a cellular phone may enter standby mode while waiting to receive an incoming call or message.
The entry of a device into a power down mode can be initiated in various ways, such as in response to a timer or in response to a processor instruction or real time interrupt. For example, a device may enter into a power down mode after it has been inactive for a preset period. Or, instruction-implemented power management may be developed to place power management under processor control. One such standard using instruction-implemented power management is the Advanced Power Management.TM. interface specification, developed jointly by Intel.RTM. and Microsoft.RTM..
One approach to processor power management is described in U.S. Pat. No. 5,584,031, entitled "System and Method of Executing a Low Powered Delay Instruction." In this approach, a special instruction specifies a number of timing cycles during which activity of a central processing unit is delayed.
Another approach to processor power management is described in U.S. Pat. No. 5,495,617, entitled "On Demand Powering of Necessary Portions of Execution Unit by Decoding Instruction Word Field Indications Which Unit is Required for Execution". An instruction coder differentiates "control" instructions from "execute" instructions. If the instruction is a "control" instruction, it does not involve the execution unit and a standby signal can be sent to the execution unit.
These known systems and methods described above have limitations and disadvantages making them unsatisfactory alternatives for achieving reduced power dissipation in some circuits.